| 摘要 |
PURPOSE:To generate surely a power-on clear signal independently of the speed of a leading time of a power supply voltage by utilizing a CMOS circuit to form the titled circuit. CONSTITUTION:When the power supply from a power supply voltage terminal 11 rises and reaches a threshold voltage of an N-channel MOSFET13, the FET13 is turned on and a potential at a point (b) falls down to a GND potential. A P- channel MOSFET14 remains turned off in this case, the level of a point (c) remains the GND level and an output terminal 17 remains at a power supply voltage level. When the level of power supply reaches a threshold voltage of the FET14, the FET14 is turned on. Since the level at the point (c) reaches the power supply voltage level, an inverter 16 is inverted and an output voltage reaches the GND level. The output voltage, that is, the power-on clear signal is generated independently of the rising speed of the power supply voltage. Thus, the power-on clear signal is generated surely independently of the speed of the rising time of the power supply voltage. |
