摘要 |
<p>Modular logic systems with a unilateral delay function and input/output facilities, as used in arithmetical and logic units of computers. They can be submitted to a step-sensitive check by feeding a test pattern into the sequential logic circuits. The same test pattern is fed via the primary inputs into a first network of combinatorial logic circuits and a matrix to produce an output pattern on the outputs of a second network of combinatorial logic circuits and a matrix to produce an output pattern on the outputs of a second network of combinatorial logic circuits following the matrix. The output pattern of the second network is put through to sequential logic circuits and their resulting state indicates whether the checked logic unit is free from defects or not.</p> |