Level sensitive embedded array logic system - has sequentially operated storage circuitry and clocked DC latches controlled by synchronous independent system clock trains

摘要

The logic system is partitioned into sections formed of combinational logic networks storage circuity, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non overlapping independent system clock trains are used to control the latches. The array is a rectangular array of storage element M X N where M is the number of words in the array and N is the number of bits in each word. A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic or an array to other latch circuitry. The clocking of the latches and of the array, are sch that the network is operated in a race free mode.