| 摘要 |
PURPOSE:To perform a multiplex processing with an arithmetic and logic circuit by carrying out successively the subtraction between each of plural constants inputted to a 1st input terminal and an optional number to be computed and inputted to a 2nd input terminal and storing the code bits of result of each operation into an accumulator. CONSTITUTION:The input numbers Xn - X1 held by a register 3 are successively inputted to an arithmetic and logic unit 4 while a fixed constant S0 is inputted to an input terminal 5. The unit 4 performs successively the subtraction of Xi - X0 as the comparison operations carried out between the input numbers Xi (i = n - 1) and the constant S0. Then the subtraction results are successively outputted from an output terminal 7 and also fed back to the register 3 and held there. At the same time, the unit 4 outputs the code bits of arithmetic results of Xi - S0 to an adder 6b. The contents of each register stage of an accumulator 6a are successively inputted to the other input of the adder 6b. The code bit 0 and 1 are outputted when the Xi - S0 are positive and negative respectively and stored in each register stage of the accumulator 6a as the stored code bit data ASn - AS1. |
