发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 PURPOSE:To attain a high-speed test for a sensing amplifier by switching the time to the shorter delay time than the usual operation time with a test mode signal, and controlling the operation of the sensing amplifier. CONSTITUTION:An (n) type MOS transistor T1 having a little conductance constant is made to be conductive state by a signal phi1 activated with an activation signal phiW and the potential of a node Q is gradually lowered. Then the (n) type MOS transistor TR TN2 is made to be conductive state previous to the TR TN1, and the potential of a contact point B is lowered. And a (p) type MOS TR TP1 having the potential of the node B as a gate input is made to be conductive state and the potential of a node A is boosted. Next, when test mode signal phiT is not activated the delay time of the signals phi1, phi2 is decided with a time constant of the state adding a capacitor C to a delay element 21. At this time the circuit becomes the normal operation state, when the signal phiT is activated, a gate TG is closed, and the time constant is reduced by the capacitor C. Consequently, the potential of the contact point B is rapidly lowered, the sensing amplifier 1 is activated at high-speed and can be tested.
申请公布号 JPH03168993(A) 申请公布日期 1991.07.22
申请号 JP19890310114 申请日期 1989.11.28
申请人 NEC CORP 发明人 NAKAYAMA HIROSHI
分类号 G11C11/409;G11C11/401 主分类号 G11C11/409
代理机构 代理人
主权项
地址