发明名称 CIRCUIT FOR PREVENTING MIS-DETECTION OF ADDRESS MARK
摘要 PURPOSE:To prevent mis-detection of an address mark by resetting the 1st latch circuit when the number ''I'' continues for a predetermined m bits or over by only adding a simple circuit. CONSTITUTION:Address mark data and a clock pulse are inputted to a flip-flop circuit 11. An output of the 1st latch circuit 52 is used as a reset signal F1 and an output of the flip-flop circuit 11 and the address mark data are ANDed and the result is fed to a flip-flop circuit 13 via an AND circuit 12. When the address mark data ''1s'' are consecutive for >=2 bits, the result is treated as a reset signal and fed to the 1st latch circuit 52.
申请公布号 JPS6124065(A) 申请公布日期 1986.02.01
申请号 JP19840143221 申请日期 1984.07.12
申请人 FUJITSU LTD 发明人 OHATA KIYOSHI
分类号 H03M13/00;G11B20/18;G11B27/10;G11B27/28 主分类号 H03M13/00
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