| 摘要 |
PURPOSE:To reduce the cell area by connecting in common four memory cells, each of which is composed of MOS transistor for a single transfer gate and capacitor for data storing, to the bit line and forming a conductive layer for gate wiring in such a manner as extending on the conductive layer which becomes the one electrode of capacitor for data storing. CONSTITUTION:Each capacitor C for data storing is formed with a capacitor plate 35 used as the one electrode and an n<-> region 34 as the other electrode. The gate wirings 41 of transistors 43a-43d for four transfer gates are formed in such a manner as extending on the capacitor plate 35 through a thick silicon oxide film 38. Thereby, it is no longer necessary to set the space for gate electrode wiring and the occupied area per cell can be reduced by that much. |
