DATA PROCESSOR AND METHOD FOR LOADING MULTI-PORT REGISTER FILE

摘要

PURPOSE: To guarantee that the latest data are used when an instruction stream is executed in a pipeline. CONSTITUTION: The register file of a pipeline microprocessor having by-pass structures 16 and 24 that drive correct source data according to the last write result is provided. Load data and execution result data 52 are returned to a RAM array in a 2nd phase of a cycle, but written in the RAM array actually in a 1st phase of the clock cycle. To evade the delay of an instruction by one cycle wherein data to be read out after being written to the RAM is held, a by-pass logic device sends the load or execution result data to be returned to the column line of the read port of a source bus in a 2nd phase of a cycle wherein the data is returned.