| 摘要 |
PURPOSE:To enable to slow down write/read operation speed keeping efficiency of a channel memory at 100% by dividing the channel memory into k divisions, writing k data corresponding to k time slots in an optional place of the channel memory dividing into k times, and at the same time, reading k data simultaneously in parallel basing on command of a counter. CONSTITUTION:Time division multiplexed data inputted from an input data highway 1 are latched by an input data latch 6 for each data of 1 time slot, and written in relevant address in a channel memory 3-i through one (8-i) of write highway 8-1-8-k. By repeating this operation k times, k data corresponding to k time slots in 1 frame are written in arbitrary address in channel memories 3-1- 3-k, and k data of the same address of channel memories 3-1-3-k are read simultaneously in parallel basing on command of an in-line reading counter 4, and latched by output data latches 7-1-7-k corresponding to channel memories 3-1-3-k. |
