发明名称 ERROR DETECTING CIRCUIT
摘要 PURPOSE:To detect not only a data error but also an error of a control circuit, etc., by dividing a circuit to be checked into plural sub-circuits, controlling separately each sub-circuit by each independent control circuit, and constituting a titled circuit so that output data of plural sub-circuits are brought to a parity check as a whole. CONSTITUTION:A circuit to be checked 3 divides and inputs data A of 8 bit (A0-A7) and its parity bit Ap, and data B of 8 bit (B0-B7) and its parity bit Bp to two sub-circuits 4 and 5, respectively. The sub-circuit 4 consists of a selecting circuit 7 of a 4 bit portion two inputting circuit and a register 9, and the sub- circuit 5 consists of a selecting circuit 8 of a 5 bit two inputting circuit and a register 10, and they are controlled independently by control circuits 1, 2, respectively. Register output signals 60, 61 of the register 9 and 10 are inputted to a parity checking circuit 6, and for instance, the number of ''1'' of the data A0- A7 and its parity bit Ap is checked, and the normal property of the data and the operation is checked.
申请公布号 JPS6120445(A) 申请公布日期 1986.01.29
申请号 JP19840140291 申请日期 1984.07.06
申请人 NIPPON DENKI KK 发明人 IZUMISAWA HIROYUKI
分类号 H04L1/00;H03M13/09 主分类号 H04L1/00
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