| 摘要 |
PURPOSE:To improve TTL compatible input characteristics without incurring the increase in current consumption and decrease in operating speed by decreasing a power supply voltage fed to an input circuit with an FET. CONSTITUTION:An nMOSFET11 is inserted between a power supply 2 and a pMOSFET5. Thus, a voltage at the source 13 of the FET5 is dropped in comparison with a threshold voltage component of the FET11 and a voltage of the power supply 2. Thus, a gate-source voltage of the FET5 when a high level input is fed from an input terminal 1 is decreased, its ON-resistance is decreased and an output of an input circuit device 10 is made closer to a ground potential. When a low-level input is fed from the terminal 1, an output of the device 10 is lowered nearly to the threshold value of the FET11 from the voltage of the power supply 2, and the detection of a high-level output is executed easily by the adjustment of size of a waveform shaping CMOS inverter 9. Further, the source voltage of the FET5 is lowered and the through-current of the FET5, 7 is decreased. |
