| 摘要 |
In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode. A selector, connected to a first stage of the shift register receives a delayed strobe command signal, and is connected to a second stage of the shift register to receive a further delayed strobe command signal, selects between the delayed strobe command signal and the further delayed strobe command signal to output a selected strobe command signal in response to the step mode control signal. A memory unit timing unit receives the selected strobe command signal, the free running clock signal, and a refresh request signal, correlates the selected strobe command signal to the refresh request signal, to output an initiate cycle signal thereby initiating the memory cycle requested by the computer system and a memory refresh cycle of the volatile memory store when the correlation occurs.
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