发明名称 |
MEMORY SYSTEM |
摘要 |
Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated. |
申请公布号 |
JPS6120166(A) |
申请公布日期 |
1986.01.28 |
申请号 |
JP19850081511 |
申请日期 |
1985.04.18 |
申请人 |
INTERN BUSINESS MACHINES CORP |
发明人 |
FUREDERITSUKU JIYON EIKERUMAN JIYUNIA;FUIRITSUPU MIIDO RAIAN |
分类号 |
G06F12/16;G06F11/07;G06F11/10 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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