Power switched logic gates

摘要

A plurality of logic gates having common data inputs are selected by activation and deactivation of switches connecting the logic gates to circuit power terminals. In one embodiment both power leads of the logic gate are connected by two power switches to two circuit power terminals. In a second embodiment, the first power lead of the logic gate is continuously connected to the first circuit power terminal and the second gate power lead is connected to the second circuit power terminal by a first power switch for a select and to the first circuit power terminal by a second power switch for a deselect. The second embodiment includes a buffer inverter on each logic gate output whose power leads are connected to the circuit power terminals as are the logic gates. Alternatively, the second switch could connect the input of the inverter to the first circuit power terminal for a deselect.