发明名称 TESTING METHOD OF LSI
摘要 PURPOSE:To reduce the number of formation processes for a test pattern by storing an input pattern for executing an instruction executing operation and its expected output patten in an instruction memory and also storing an input pattern corresponding to an even and its expected output pattern in a pattern memory. CONSTITUTION:An instruction and data for checking the instruction executing operation of a microprocessor 110 and an expected output pattern obtained when the processor 110 executes a prescribed instruction are stored in the instruction memory 121 and an input pattern obtained at the generation of an event from the processor 110 and an expected output pattern corresponding to the input pattern are stored in the pattern memory 102. When the prescribed instruction is outputted from the memory 121, the instruction pattern of the processor 110 and the expected output pattern outputted from the memory 121 are inputted and compared to/by an expected value comparator 105 and the even input pattern outputted from the memory 102 is also compared with the expected output pattern outputted from the processor 110 by the comparator 105.
申请公布号 JPS6120144(A) 申请公布日期 1986.01.28
申请号 JP19840140504 申请日期 1984.07.09
申请人 HITACHI SEISAKUSHO KK 发明人 SATAKE SHIYOUZOU
分类号 G11C29/00;G01R31/28;G01R31/319;G06F11/22;G11C29/56 主分类号 G11C29/00
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