发明名称 PHASE LOCKED LOOP
摘要 PURPOSE:To obtain a high-speed phase locking without hang-up phenomena by providing hysteresis characteristics having two ways of phase comparison outputs in response to the history of phase change except points before and after locking stable point to a phase comparator. CONSTITUTION:The phase between an input signal and an output of a voltage controlled oscillator 2 is compared by a phase comparator 3', a signal via a loop filter 4 of the compared output controls the oscillator 2 to phase-lock the input signal and the signal from the oscillator 2 and the result is outputted from a terminal 5. In this case, when the phase difference theta between the input signal and the output signal of the oscillator 2 is within the range of -pi/2-+pi/2, the comparator 3' shows an output characteristic of sintheta, and when the theta is within the range of pi/2-3pi/2, +1 is outputted and when in the range of -3pi/2--pi/2, -1 is outputted by the hysteresis characteristic. Thus, when the phase difference theta is within -3pi/2-+3pi/2, the phase is slipped in the direction of the arrow in the figure and the output is converged to the zero point.
申请公布号 JPS6118220(A) 申请公布日期 1986.01.27
申请号 JP19840137269 申请日期 1984.07.04
申请人 KOKUSAI DENSHIN DENWA KK 发明人 OOKAWA NORIHISA;KOBAYASHI HIDEO
分类号 H03L7/10;H03L7/085;H03L7/087;H04L27/227 主分类号 H03L7/10
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