发明名称 MULTILAYER INTERCONNECTION MEMBER
摘要 PURPOSE:To equalize thickness of interlayer insulation film formed by the quartz bias sputter technique at the upper part of lower layer wiring for connection between elements and at the upper part of lower layer wiring for power supply by providing a pedestal at the lower part of lower layer wiring for power supply. CONSTITUTION:A pedestal 3 is formed with a conductive layer of the 1st layer formed on the field insulation film 2 at the upper part of main surface of semiconductor substrate 1. This pedestal 3 may be formed, for example, in the thickness of about 0.6mum using the polycrystalline silicon layer, high melting point metal layer or silicide layer, etc. Next, an insulation film 4 is formed and a lower layer wiring 5A for inter-element connection and a lower wiring layer 5B for power supply are formed by conductive layer of the 2nd layer on said insulation film 4. Next, an insulation film 6 is formed. This insulation film 6 can be formed in the thickness of about 1.2mum as in the case of the upper part of the lower wiring 5A for inter-element connection due to the existence of the pedestal 3. The insulation film 6 on the lower wiring 5A for inter-element connection and the lower wiring 5B for power supply is removed selectively and connection holes 7A, 7B are formed. Since the thickness of insulation film 6 is equalized, these connection holes 7A, 7B facilitate etching control in the depth direction thereof.
申请公布号 JPS6118152(A) 申请公布日期 1986.01.27
申请号 JP19840137182 申请日期 1984.07.04
申请人 HITACHI SEISAKUSHO KK 发明人 MURATA JIYUN;FUJITA MINORU
分类号 H01L23/522;H01L21/768 主分类号 H01L23/522
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