| 摘要 |
PURPOSE:To increase the inter-picture element arithmetic processing time by using a clamping circuit which selects and delivers the arithmetic result of an arithmetic logical operation ALU or the clamp data as the output data and also delivers the complement signal. CONSTITUTION:A decoding circuit 20 in a clamping circuit 14 decodes the arithmetic mode information M of an ALU13, a carry bit C, the highest bit A of the arithmetic result, a sign bit S of the 2nd picture data held by a register 12 and the expression condition N and delivers a complement signal 15 as well as selection control signal 22-24 to be sent to a selector 21. The selector 21 selects either one of the arithmetic result l of the ALU13, the over-clamp data (m) containing all bits set at logic 1 and the under-clamp data (n) containing all bits set at logic 0. A selector 17 selects and delivers the output data given from a complement circuit 16 or the coupled information (C+q) of the carry bit C given from the ALU13 and a bit (q) excluding the lower bit of the result l as the 3rd picture data. |
