| 摘要 |
PURPOSE:To improve the throughout of a common bus as well as the processing efficiency by performing a buffer access of the transfer B between the buffer accesses of the transfer A and the next transfer A. CONSTITUTION:A buffer access request delivered from the buffer access request part 10 for transfer B is prevented by an AND gate 13 when the gate signal is ON and not informed to a buffer access control part 11. In this case, a gate signal generating part 12 detects previously the delivery of a buffer access request signal for transfer A by a signal SFXD (showing a fixed fact to use a common bus next) given from a common bus using right control part 8. The part 12 keeps the gate signal OFF just for a cycle before the output of the signal SFXD, e.g., immediately before the end of the buffer access of the transfer A. Thus the buffer access request is permitted for the transfer B. This improves the throughout of a common bus 1 as well as the processing efficiency. |
