发明名称 RECEIVER
摘要 PURPOSE:To detect a signal from a demodulation output under a low S/N by sampling a signal 1-bit by several samples and comparing the bit series with a code from a code generator without forming a bit synchronizing signal. CONSTITUTION:The output of an FSK demodulating circuit 10 is sampled by a sampling device 22 not by signal one bit length but by, e.g., 8 samples. A data outputted from the sampler 22 is inputted sequentially to a shift register 24, 8 data are extracted from the register 24 at the interval of 8 samples and inputted to a comparator 21. The comparator 21 compares a code to be compared and collated every input of one sample with an input signal string and as the result of the comparison, if majority or over is coincident, it is decided that the signal is detected.
申请公布号 JPS6115448(A) 申请公布日期 1986.01.23
申请号 JP19840135611 申请日期 1984.06.29
申请人 MATSUSHITA DENKI SANGYO KK 发明人 NAGAISHI YASUO;HORIIKE YOSHIO;FUKUI KIYOTAKE
分类号 H04L25/40;H04L7/08;H04L25/06 主分类号 H04L25/40
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