发明名称 WIRING NETWORK CONSTRUCTION OF INTEGRATED
摘要 PURPOSE:To reduce wiring capacity and wiring resistance, to enable reducing the area of a chip and to contrive the higher speed of circuit operation by connecting the wiring in the same wiring layer with the same conductor within each group wherein wiring is possible without crossing. Each of the divided plural groups is a collection of wiring groups. CONSTITUTION:The first layer wiring 1 is connected with a contact part 23' provided on an element terminal part such as an impurity diffusion layer 21 on the surface of an integrated circuit substrate 20 and on an insulation film 22 on the surface of the substrate. For example, it is the first aluminum wiring 23 group. The second layer wiring 2 is a metal wiring group formed on an interlayer insulation film on the first layer wiring 1. In this case, the connection between the second layer wiring 2 and an element terminal part B is made by connecting a metal wiring 25 and the contact part 23' for the second layer wiring formed at the same time with the forming process of the first layer wiring 1 a through hole 25' being formed in an interlayer insulation film 24 on the contact part 23'.
申请公布号 JPS6170738(A) 申请公布日期 1986.04.11
申请号 JP19840192171 申请日期 1984.09.13
申请人 TOSHIBA CORP 发明人 KOIKE MITSUHIRO
分类号 H01L21/3205;H01L23/52;(IPC1-7):H01L21/88 主分类号 H01L21/3205
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