| 摘要 |
PURPOSE:To prevent an element from damaging due to an overcurrent by monitoring the gate signal pattern of a PWM inverter, and breaking a gate signal when an abnormal pattern is detected for the prescribed time. CONSTITUTION:A pulse of the prescribed frequency is output from a V/F converter 20, and applied to a PWM signal forming circuit 21. The pulse is converted by the circuit 21 into a 3-phase AC, and compared with a triangular wave to become PWM signals Eu, Ev, Ew. The signals Eu-Ew are applied to a decoder 22, the same phase is detected, and a resetter 24 resets a counter 25 at every varying point of the same mode. The counter 25 counts clocks 27 at the same mode time, and when the same phase mode continues, the output is fed to a latch 26 after counting as prescribed. The latch 26 generates an output (h) to close a gate 29, and the output of a gate logic circuit 28 is interrupted. |
