| 摘要 |
PURPOSE:To enhance the protection power by a method wherein the gate voltage of a MOS-FET to be protected is kept at a voltage below the drain-source withstand voltage BVDS, and the conduction resistance of the MOS-FET to be protected is reduced when the overvoltage is large. CONSTITUTION:The potential between the protection resistor R2 and the gate of the N type MOS-FETQ3 to be protected is divided by capacitors C1 and C2, and the result is supplied to the gate of an N type MOS-FETQ4; thus, the capacitances of the capacitors C1 and C2 are set in such a manner that the MOS- FETQ4 is not conducted during normal action. In the case of C1=0.1pF and C2=1.0pF, when an input terminal B comes into a voltage over 6.6V, the MOS- FETQ4 becomes conducted and starts discharge. However, when a point 2 comes into an increase in voltage, e.g. 18V, a point 3 comes into a voltage of 1.63V, and the gate voltage increases substantially, resulting in the enhancement of protection power. |
