| 摘要 |
PURPOSE:To enhance the integration degree by processing to overlap the patterns of power terminals of adjacent circuit cells when the power terminals of the two circuit cells are disposed adjacent, and commonly providing the power terminal for the adjacent cells on a real pattern, thereby holding the advantage of the standard cell type. CONSTITUTION:A cell 1 is a 3-input NAND and a cell 2 is a 4-input NAND, and the cells 1, 2 are partly superposed. The superposed region is power terminals 1, 2 for connecting power sources VDD and VSS to a semiconductor substrate, and even if commonly provided at adjacent cells, no defect occurs in funtion. The cells may be superposed as the common standardized pattern between different type cells, and information for indicating the terminal is added to the pattern information and registered in advance in a library. When two cells are adjacently disposed, the standardized power terminals are superposed, but this process is similar to the conventional standard cell type to perform without returning to the pattern in the cell.
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