发明名称 Noise reduction circuit for video signal.
摘要 <p>A noise reduction circuit for a video signal comprises a plurality of circuit parts (31 A - 31 C) coupled in series and a control circuit (32). Each of the circuit parts comprise a delay circuit (34, 39, 40) for delaying an input video signal supplied thereto, a first subtracting circuit (35A - 35C) for subtracting an output signal of the delay circuit from the input video signal, a limiter circuit (36A - 36C) for limiting the amplitude of an output signal of the first subtracting circuit, and a second subtracting circuit (38A - 38C) for subtracting an output signal of the limiter circuit from the input video signal and for producing a signal which is reduced of a noise component within the input video signal. The delay circuit in each of the circuit parts has a different delay time in accordance with a kind of correlation existing in information contents of the input video signal. The control circuit comprises a plurality of detecting circuits (42A - 42C) provided in correspondence with the circuit parts and a control signal supplying circuit (44a - 44c, 43a - 43f). Each of the detecting circuits a supplied with the output signal of the first subtracting circuit of a corresponding circuit part and detects large amplitude signal components thereof.</p>
申请公布号 EP0169052(A2) 申请公布日期 1986.01.22
申请号 EP19850305053 申请日期 1985.07.15
申请人 VICTOR COMPANY OF JAPAN, LIMITED 发明人 ICHINOI, YUTAKA
分类号 H04N5/213;H04N5/21 主分类号 H04N5/213
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