发明名称 Timing control system in data processor
摘要 This invention relates to a timing control, for example, a control for reserving a waiting time when a data processor sends or receives data to or from an external device. Dummy cycles for a number of cycles having a processing time equal to the desired waiting time are generated by a dummy instruction. A timing control system is disclosed which is especially suitable for a micro-program system of a pipeline control system.
申请公布号 US4566062(A) 申请公布日期 1986.01.21
申请号 US19830508503 申请日期 1983.06.28
申请人 FUJITSU LIMITED 发明人 OHNISHI, KATSUMI;MIZUSHIMA, YOSHIHIRO;SATO, KIYOSUMI
分类号 G06F9/22;G06F9/30;G06F9/38;(IPC1-7):G06F9/00 主分类号 G06F9/22
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