发明名称 DISCRIMINATION SYSTEM FOR DIGITAL SIGNAL LEVEL
摘要 PURPOSE:To vary a threshold voltage following up abrupt variation in input digital signal level and to discriminate a signal level accurately by detecting a wrong bit in the bit array of a digital signal whose signal level is discriminated according to the regularity of the array, and then switching level discriminating means according to the detection result. CONSTITUTION:Bit error detection outputs ''1'' of detection output AND circuits ADa and ADb are ORed by an OR circuit ORC, whose output is supplied to a multivibrator MV. Then, a time constant circuit R.Ca is set properly, and when the detection output ''1'' is supplied to the multivibrator MV, the Q output of the multivibrator MV connects a level ''1'' for a period of about 10 bits; and the Q output ''1'' is supplied to the inverted input terminal of the output AND circuit ADbn of a simplified correcting circuit and the other output AND circuit ADan in parallel. Then, level discrimination outputs of a couple of comparators CP1 and CP4 for normal operation and comparators CP2 and CP3 for a drop state are led to those output AND circuits through respective OR circuits OR-1 and OR-2 and (n) stages of 1-bit shift registers Da-1-Da-n and Db1-Db-n. Consequently, practically accurate signal level discrimination is performed through the simple circuit constitution.
申请公布号 JPS6113478(A) 申请公布日期 1986.01.21
申请号 JP19840132942 申请日期 1984.06.29
申请人 NIPPON HOSO KYOKAI 发明人 NAKAGAWA SHIYOUZOU
分类号 G06F11/00;G11B20/10;G11B20/18 主分类号 G06F11/00
代理机构 代理人
主权项
地址