发明名称
摘要 PURPOSE:To increase processing performance by eliminating the time of an ineffective scan by selecting a circuit group with the highest priority level among respective groups during a circuit scan by dividing circuits, differing in communication rate, into groups and by previously storing the top priority processing circuit number for requests for processing. CONSTITUTION:Circuit coordinating circuits 21 of circuits differing in communication rate are divided into the 1st-(n)-th groups; and storage 10 for a table is provided previously with areas for the 1st group the (n)-th group and in each area, an in-group circuit number, priority level specifying information, in-group circuit number effective specifying information, and final-group specifying information are inputted from signal line 16 and stored. During a scan, a request-for-processing signal from each group is applied to address register 11 for the table via request-for- processing signal line 18 and on the basis of its address, access to storage 10 is attained to select the in-group top-priority circuit in every group by utilizing buffer register 14 for comparison. Further, the top-priority circuits in respective groups are compared mutually to select single circuit 21 with the highest priority level, thereby increasing the processing performance.
申请公布号 JPS611949(B2) 申请公布日期 1986.01.21
申请号 JP19800057648 申请日期 1980.04.30
申请人 FUJITSU LTD 发明人 OGAWA YOSHIHISA;SADAKUNI JUJI;ODAKAWA TOSHUKI
分类号 H04L29/04;G06F13/00;G06F13/22 主分类号 H04L29/04
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