发明名称 MASTER SLICE TYPE GATE ARRAY DEVICE
摘要 PURPOSE:To obtain the prescribed characteristics as well as to enhance the operating efficiency of an element by a method wherein an MOS transistor, having the element size equivalent to that of the MOS transistor provided inside a basic cell part, is provided inside of a plurality of input cell parts provided on the circumferential part of a semiconductor chip. CONSTITUTION:An input-output pad 13, a resistor 14 and a diode 15 to be used for input protector, a number of P-channel MOS transistors 16 to be used to constitute an input-output buffer and the like, and an N-channel MOS transistor 17 are provided. Also, P-channel MOS transistors QP1 and QP2, provided in a basic cell 10, N-channel MOS transistors QN1 and QN2, a plurality of P-channel MOS transistors 31 and N-channel MOS transistors 32, having the same element size, namely, the channel width W and the channel length L, are newly provided.
申请公布号 JPS6112043(A) 申请公布日期 1986.01.20
申请号 JP19840132336 申请日期 1984.06.27
申请人 TOSHIBA KK;TOUSHIBA MAIKON ENGINEERING KK 发明人 YAMAGUCHI KAZUO;ISHII KENJI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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