发明名称 MASTER SLICE TYPE SEMICONDUCTOR DEVICE
摘要 <p>PURPOSE:To enable to naturally perform a wire bonding for connection of the lead provided in extended form outside a package and electrodes by a method wherein a plurality of electrodes are evenly arranged on the circumference of a plurality of input-output circuits provided on the circumference of a semiconductor chip, and a wiring region to be used for connection of said electrodes is provided. CONSTITUTION:A plurality of input-output circuits 32, 32... are provided along the circumference of the surface of a master slice IC 31, and a plurality of electrodes 33, 33... are evenly arranged on the circumference of said input-output circuits 32, 32.... A plurality of leads 34, 34... are arranged on the circumference of the master slice 31 parting from it. The other end side of the leads 34, 34... is extended to outside of a package 15. Also, a wiring region 35 is provided between the electrodes 33, 33... on the master slice IC 31 and the input-output circuits 32, 32.... The electrodes 33, 33... are connected to the leads 34, 34... through the intermediaries of bonding wires 37, 37... respectively.</p>
申请公布号 JPS6112042(A) 申请公布日期 1986.01.20
申请号 JP19840132309 申请日期 1984.06.27
申请人 TOSHIBA KK 发明人 FUJIWARA YOSHIAKI
分类号 H01L23/50;H01L21/82;H01L27/118 主分类号 H01L23/50
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