发明名称 HARDWARE DIVIDER
摘要 PURPOSE:To perform a division at a high speed by executing the addition/ subtraction and a left-shoft operation just with hardware. CONSTITUTION:A dividend of (N+n) bits and a divisor of N bits are supplied through a divider. Then the divider delivers the quotient of (n) bits, the overflow of 1 bit and the residue of N bits. The plural units of general N-bit parallel adders/subtractors 12 are provided to the divider. The adder/subtractor 12 consists of an N-bit dividend input terminal A, an N-bit divisor input terminal, a 1-bit action command output terminal I, an N-bit arithmetic output terminal Z and a division overflow output terminal C to which the signal equal to the highest bit of the terminal Z is delivered. Then the adder/subtractor 12 performs the addition or the subtraction in response to the signal supplied to the terminal I.
申请公布号 JPS6175926(A) 申请公布日期 1986.04.18
申请号 JP19840197937 申请日期 1984.09.21
申请人 TOSHIBA CORP 发明人 OZAKI TAKAYUKI
分类号 G06F7/537;G06F7/52;G06F7/535 主分类号 G06F7/537
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