| 摘要 |
PURPOSE:To enable the increase in withstand voltage, and to contrive speed-up by reducing the capacitance of drain junction, by a method wherein a drain region surrunded by a polycrystalline Si gate is provided with an impurity layer of reverse conductivity type to that of a substrate which is the internal region distant from a gate electrode, and with an impurity layer of lower impurity concentration which surrounds that inpurity layer. CONSTITUTION:The polycrystalline Si gate electrode 6 is formed in ring form, and the part outside the ring is the source region II, and inside is the drain region I. As a result, the drain region is in the form of being surrounded by the polycrystalline Si gate. Then, the drain region is constructed by forming the impurity region 9 of revers conductivity type to that of the substrate which is the internal region distant from the gate electrode and the same impurity concentration as the source region and by forming over the drain region the impurity layer 11 deeper than the impurity layer 9 and having a lower impurity concentration. A marked improvement in withstand voltage can be attained by such an independence of the concentration of a channel stopper and by no inclusion of edges of the diffused layer. |
