发明名称 VERTICAL DEFLECTION SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To discriminate accurately the presence of a vertical synchronizing signal by providing a timer circuit and detecting its output signal if it does not exist even after a prescribed period or over and applying a drive pulse to generate a pseudo sawtooth waveform at the same time. CONSTITUTION:A signal fed to an input terminal 13 of a vertical synchronizing signal is inputted to the timer circuit 15 through a gate circuit 14. An output of the timer circuit 15 is inputted to the timer circuit 15 through a gate circuit 14. The output of the timer circuit 15 enters the base of a transistor (TR)17 through a resistor 16. A collector of the TR17 is connected to a charge capacitor 18 and a constant current source 19 generating a sawtooth wave. The output of the timer circuit 15 is fed to a TR23 through resistors 21, 22. A timing resistor 24 and a capacitor 25 are connected to the collector of the TR23 and a connecting point between the resistor 24 and the collector is connected to an inverter 26. An output terminal of the inverter 26 is connected to other input terminals of the gate circuit 14.
申请公布号 JPS6110367(A) 申请公布日期 1986.01.17
申请号 JP19840131350 申请日期 1984.06.26
申请人 MATSUSHITA DENKI SANGYO KK 发明人 OKAMURA YUKIMICHI
分类号 H04N5/08;H04N3/16 主分类号 H04N5/08
代理机构 代理人
主权项
地址