| 摘要 |
PURPOSE:To eliminate a deadlock and to ensure a normal access action by providing a deadlock release circuit which invalidates temporarily the BUS control signal delivered from a CPU after detecting a deadlock and delivers an internal BUS to another master. CONSTITUTION:When both an external BUS request signal MBRQb and an internal BUS request signal INBRQc are delivered, a deadlock detecting circuit 18 sets a flip-flop of a deadlock release circuit 20. Then both address and data BUSes are invalidated by an input/output valid signal *ENAOi. Then the circuit 20 delivers an internal BUS occupation right switching signal *AVCHGh. Thus a BUS arbiter 19 delivers an occupation allowance signal BSAVod of the internal BUS and delivers the occupation right of the internal BUS to another master. An internal BUS timing control circuit 17 produces a series of internal BUS control signals. Then the flip-flop is reset when an access is over, and the BUS control signal is recovered at the internal BUS. |
