| 摘要 |
<p>In a data processor adapted to perform operations upon operands of a given size, a bus controller (14) is provided to communicate the operands with a storage device (20) having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller (14) requesting the transfer of an operand of a particular size, the storage device (20) provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the torage device (20), the bus controller (14) may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller (14) compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller (14) provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.</p> |
