THREE WORD INSTRUCTION PIPELINE

摘要

Pipelined data processing systems which have deep pipelines normally operate at a disadvantage because of consuming excess access time during normal operation which is exacerbated when a branch operation is called for which necessitates a refilling of the pipeline. In order to minimize the above enumerated disadvantage, a data processor which uses a three word instruction pipeline composed of registers (32, 34/36 and 38/40) provides early decoding of instructions from a store (12 and 14) by decoders (18, 20, 22, 24 and 26) requiring only two bus access cycles to fill the pipeline because of the operation of its execution unit (10). Two of the three words required to fill the pipeline are fetched in a single one of the bus access cycles, and all of the registers making up the pipeline are reset simultaneously when a branch operation requires the refilling of the pipeline.