发明名称 FORMING METHOD OF MULTILAYER WIRING
摘要 PURPOSE:To form the multilayer wiring of a semiconductor integrated circuit characterized by excellent flatness and high reliability, by using a double-layer structure, in which a plasma nitride film is deposited and a sputtered oxide film is further etched thereon, as an insulating film between metal wirings. CONSTITUTION:A nitride film 204 is deposited on a first-layer aluminum wiring 203. A sputtered oxide film 205 is deposited thereon by applying a high-frequency bias on a semiconductor substrate. Thus the surface is flattened. Then the surface is coated by a photoresist film 206. A selective opening part is provided in the photoresist film 206. The silicon oxide film 105 on an interlayer insulating film is etched by buffered fluoric acid with the photoresist 206 as a mask. The etching is stopped at the upper part of the silicon nitride film because the etching speed of the lower silicon nitride film 204 is extremely slow. The silicon nitride film 204 is removed by anisotropic etching. An opening part 207 with depth reaching the first aluminum wiring layer 203 is provided. Then the photoresist film 206 is removed, and a second layer aluminum wiring layer 208 is provided. Finally heat treatment is performed.
申请公布号 JPS618954(A) 申请公布日期 1986.01.16
申请号 JP19840130455 申请日期 1984.06.25
申请人 NIPPON DENKI KK 发明人 YAMADA YOSHIAKI
分类号 H01L21/3205;H01L21/768 主分类号 H01L21/3205
代理机构 代理人
主权项
地址