DIGITAL SIGNAL PROCESSOR

摘要

The signal processing arrangement is an adaptive digital filter comprising a digital filter coefficient updating circuit (CUC) which supplies updated filter coefficients to a digital filter circuit proper (FC) and is controlled by an error signal (E) derived from the output signal of the filter proper. Each of these two circuits (CUC, FC) is constituted by a systolic processor with a plurality of interconnected cells each able to calculate a function of the type mn + p in a bit serial way and in such a way that bits of a same rank are successively calculated in the cells starting from right to left.