发明名称 CACHE DISABLE FOR A DATA PROCESSOR
摘要 <p>A data processor (300) is adapted for operation with a memory (305) containing a plurality of items of operating information for the data processor (300). In addition a cache (301) stores a selected number of all of the items of the operating information. When the cache (301) provides an item of operating information, the memory (305) is not requested to provide the item so that a user of the data processor (300) cannot detect the request for the item. A disable circuit is provided to prevent the cache (301) from providing the item when a signal external to the data processor (300) is provided. Consequently, a user, with the external signal, can cause the data processor (300) to make all of its requests for items of operating information to the memory (305) where these requests can be detected.</p>
申请公布号 WO1986000440(A1) 申请公布日期 1986.01.16
申请号 US1985000657 申请日期 1985.04.12
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