| 摘要 |
PURPOSE:To detect suitably the discrimination of synchronization and asynchronization by applying synchronous detection to a clock signal detected by a phase locked loop to an input signal at a phase of 0 deg. and 90 deg. and comparing the output. CONSTITUTION:An intermediate frequency IF signal of a receiver is impressed to a phase comparator 1 of a PLL circuit, an IF signal and clock signals (c), (d) having a phase difference of 0 deg. and 90 deg. respectively from a VCO circuit 3 are detected and they are inputted respectively to a 0 deg. synchronous detection circuit 5 and a 90 deg. synchronous detection circuit 6. A signal(a) detected by the circuit 5 includes a sub signal L+R of right, left channels CH, a signal (b) detected by the circuit 6 includes a difference signal L-R of the right, left CH and they are inputted respectively to an unlock circuit 7. When the PLL circuit is synchronized with the I//F signal, an output signal (e) of the circuit 7 throws the switch circuit 8 to the position B, the signals a, b are inputted to a matrix circuit 9, from which L, RCH signals are outputted respectively. When the PLL circuit is not synchronized with the IF signal, the output (e) of the circuit 7 throws the circuit 8 to the position A and a monaural signal is outputed from an envelope detection circuit 4. |
