发明名称 SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To obtain the cell of one element/bit for the high integration of an EEPROM by changing the electric potential of a data line above an external electric power source or below 0V when reading the information of a memory cell. CONSTITUTION:A pulse generated by the change of the address of an address buffer 81 is outputted from a control circuit 82 to a signal line 83 for bootstrap and charges a data 86 selected by a Y decoder 84, a Y switch 85 above 5V, for example to 7V by the bootstrap. The charged data line is changed in electric potential by the condition of a memory cell selected by an X decoder 88 (memory array 89). This signal change is detected by a sense amplifier 90 and outputted through an output buffer 91 to the outside. Thereby, the memory cell can be constituted with one element of a memory transistor capable of taking threshold voltages of a positive and a negative, and even if the threshold voltage of the transistor of a non selecting memory cell belonging to the same data line is negative, the information of a selecting cell can be correctly read.</p>
申请公布号 JPS6177196(A) 申请公布日期 1986.04.19
申请号 JP19840196626 申请日期 1984.09.21
申请人 HITACHI LTD 发明人 TANIDA YUJI;HAGIWARA TAKAAKI;SHIMOHIGASHI KATSUHIRO;MINATO OSAMU;KUBO SEIJI
分类号 G11C17/00;G11C16/04;H01L27/10 主分类号 G11C17/00
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