| 摘要 |
A structure associating a high current NPN transistor with a PNP control transistor also able to withstand relatively high currents in an integrated circuit structure. This structure comprises an N+ type substrate overlaid by a P type epitaxied layer and a second N type epitaxied layer. The PNP transistor is disposed in the center of a region defined by two successive peripheral isolating walls. The NPN transistor is disposed in the annular zone. In this zone, the N+ substrate and the N layer are connected together by a buried N+ type layer locally short-circuiting the P type layer along a ring, thus isolating the central part of this layer at the level of the PNP transistor.
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