| 摘要 |
The computer system of this invention has, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. A reset switch is operable by the operator of the computer system to reset the system by forcing the CPU to a known address. Also, at power-up, the CPU is reset starting at a preselected address. The CPU may also be restarted by means of the manual reset switch starting with execution of instructions from a predetermined address in the ROM. The reset switch couples to the interrupt input of the microprocessor. The power-up circuit couples to the reset input of the microprocessor.
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