| 摘要 |
PURPOSE:To implement data shorter than a unit time so as to make the data highly accurate, by dividing phase shifting data into high-order and low-order bits and phase-shifting the phase data by the quantity of the unit time only when overflow occurs by integrating the low-order bit. CONSTITUTION:Set phase data C are divided into high-order bits H and low- order bits L and the high-order bit H and low-order bits L are supplied to the A-width circuit 9 of a digital phase shifter and integration circuit 12, respectively. Moreover, output signals a' differentiated at a differentiation circuit 8 are also supplied to an integration circuit 12 and integration is performed at every time when the signals a' are inputted. If overflow occurs in the course of integration, a signal (j) is supplied to a delay circuir 13. In addition, the output of the circuit 9 is supplied to a differentiation circuit 10 and the differentiated output h' of the circuit 10 is supplied to the circuit 13 where the output h' is delayed by one clock time at every time when the signal (j) is inputted. The output signal h'' of the circuit 13 is supplied to a B-width circuit 11. The data shorter than a unit time are implemented so as to make the data highly accurate, by phase-shifting the data of the low-order bits L by the unit time quantity only when overflow occurs. |
