发明名称 CONTROL SYSTEM OF TAG STORAGE DEVICE
摘要 PURPOSE:To reduce a processing load of a CPU in case of a buffer nullification processing by providing a means for detecting a fault in a tag storage device, and a means for setting separately a way containing a fault detected by said means to an unavailable state. CONSTITUTION:Control lines 60-0-60-15 are outputs of a parity error display bit of a register of a TAG2 of a main storage access control device 3, and inputted to an OR gate 61 and AND gates 64-0-64-15, as signals for showing the generation of a parity error of each way, respectively. An output of the gate 61 is inputted to a counter 62, and when one line of the control lines 60-0-60-15 displays an error and turns on, the counter 62 adds ''1'', and when a counting value becomes a prescribed value, a control line 63 turns on. In this case, by outputs of the AND gates 64-0-64-15 to which the controls lines 60-0-60-15 having an error display are connected, corresponding latches 65-0-65-15 are set to on.
申请公布号 JPS617959(A) 申请公布日期 1986.01.14
申请号 JP19840128617 申请日期 1984.06.22
申请人 FUJITSU KK 发明人 ISHIDA MIYUKI;CHIBA TAKASHI
分类号 G06F12/08 主分类号 G06F12/08
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