发明名称 LAYOUT METHOD OF INTEGRATED CIRCUIT
摘要 PURPOSE:To minimize correction work even through the driving-capacity optimizing layout of circuit blocks, to reduce correction work to several times and to decrease man-hours on work by selecting and replacing circuit blocks having the different driving capacity of buffers from the group of circuit blocks in response to the load capacity of an integrated circuit at the ratio of 1:1. CONSTITUTION:A circuit block 10 is arranged, wires are wired, and an intermediate circuit block 20 is shaped. Similar intermediate circuit blocks 20-23 are disposed, and wires are wired, thus forming the last circuit block 30. The load capacity of the integrated circuit is classified, and blocks having the different driving capacity of buffers are replaced in response to load capacity at the ratio of 1:1. An output terminal Y for the circuit block 10 must drive gates for extremely many circuits at the level of the circuit block 30, but it can correspond to them only by correcting transistors for buffer circuits. The method can correspond even to a demand reducing the number of elements by replacing circuit blocks in which buffer circuit sections are removed when load capacity is sufficiently small, and the layout of a chip need not be corrected.
申请公布号 JPS616850(A) 申请公布日期 1986.01.13
申请号 JP19840127773 申请日期 1984.06.21
申请人 NIPPON DENKI KK 发明人 TAKEGAWA TOUJIROU
分类号 H01L21/822;H01L21/82;H01L27/02;H01L27/04 主分类号 H01L21/822
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