| 摘要 |
PURPOSE:To reduce the scale of circuits by adding the serial data on the multiplicand every bit in response to each digit bit of the multiplier. CONSTITUTION:A multiplicand A is supplied to a parallel/serial conversion (P/S) circuit 1; while a multiplier B is stored in a register 2 in the form of the parallel data. The least significant bit of the multiplier B given from the register 2 is supplied to a gate G1 together with the output (a) of the P/S circuit 1. When the least significant bit of the multiplier B is equal to 1, the value of the multiplicand A is delivered as it is and supplied to a 1-bit adder circuit 3. While the output of the gate G1 is equal to 0 when the least significant bit of the B is set at 0. Then the serial data (b) on the A which is delayed by a bit from the timing of the output (a) of the circuit 1 is supplied to a gate G2 together with the 2nd bit data from the least significant bit of the B. The output of the gate G2 is supplied to the circuit 3. The result of addition obtained from low-order 2 bits of the B is outputted serially from the circuit 3. |
