发明名称 |
PHASE DETECTOR AND PLL CIRCUIT WITH SAME PHASE DETECTOR |
摘要 |
A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse. |
申请公布号 |
JPS614326(A) |
申请公布日期 |
1986.01.10 |
申请号 |
JP19850125260 |
申请日期 |
1985.06.11 |
申请人 |
PHILIPS' GLOEILAMPENFABRIEKEN NV |
发明人 |
JIYON MIRUTON YARUBOROO |
分类号 |
H03L7/085;H03D13/00;H03L7/087;H03L7/113;H03L7/14 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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