| 摘要 |
PURPOSE:To facilitate the future extension of the microcomputer syste by equalizing the period from the generation to the ceasing of a reception signal to the specific time width of a memory ready signal. CONSTITUTION:When a decoder 8 outputs a select signal CS, a corresponding memory ready control circuit 9 outputs the L-level Q output of an FF1 to an MPU1. Then, when the decoder 8 outputs a select signal CS1, the CS1 is sensed at the rise of an E clock E1 after the rise of the CS1 and the FF outputs 1 and also output ''0'' as its Q output. The MPU1 on knowing that MRDY falls to the level L performs processing as to the E clock E1. At the same time, the Q output of the FF1 is fetched in an FF2 at the rise of a system clock after the rise of the E clock E1, and then transferred to an FF3 and an FF4 in order in synchronism with the rise of the system clock. |
