发明名称 COMPLEMENTARY MOS SEMICONDUCTOR DEVICE
摘要 PURPOSE:To prevent latch up by a method wherein the title device is so constructed that a P type polycrystalline Si electrode denser than a well region is present in a groove shallower than the well in the P-well region. CONSTITUTION:A P-well region 12 is formed by injecting boron to N type Si substrate 11. Next, channel stoppers 13 and 14 are formed by injecting boron denser than that of the P-well to the part serving as a field region in the P-well region 12, thereafter, a field 15 is formed. Gate oxide films 16 and 17 are formed, and polycrystalline Si layers are formed thereon, thus forming gate electrodes 18 and 19. Further, P type diffused layer regions 22, 23 are formed on the substrate 11, and N type diffused layer regions 20 and 21 are formed on the P- well region 12 by self-alignment. An oxide film 24 is formed, and grooves 25 and 26 shallower than the region 12 are formed. Then, P type polycrystalline Si layers doped with boron denser than that of this well region. Besides, a phosphorus glass layer 29 is formed, and a metalic wiring 30 is deposited.
申请公布号 JPS613448(A) 申请公布日期 1986.01.09
申请号 JP19840123221 申请日期 1984.06.15
申请人 NIPPON DENKI KK 发明人 AKIYAMA HIROAKI
分类号 H01L27/08;H01L21/761;H01L21/8238;H01L27/092 主分类号 H01L27/08
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